Chapter Summary

Chapter 16: RIS Prototyping and Measurements — Summary

Key Points

• 1.

  RIS prototypes at sub-6 GHz, mmWave, and sub-THz achieve measured SNR gains of 12–21 dB — consistent with theoretical $N^2$ scaling minus hardware losses

• 2.

  The 4–6 dB gap between ideal and measured gain is driven by: 2-bit quantization (-0.9 dB), PIN-diode loss (-1.5 dB), off-broadside incidence (-1 to -3 dB), polarization (-0.2 dB), and residual calibration error (-0.1 to -1 dB)

• 3.

  Calibration is mandatory: uncalibrated panels lose 10+ dB of coherent gain. Per-element LUT maps commanded phase to bias voltage; thermal drift requires periodic refresh (30 min outdoor)

• 4.

  The Gaussian phase-error model gives $\mathbb{E}[G_{\text{BF}}] = N + N(N-1) e^{-\sigma_\phi^2}$ — a direct design budget from calibration accuracy to coherent gain

• 5.

  OTA codebook characterization with $M \approx 10^3$ patterns is the practical sweet spot; continuous-phase scan ($N K$ samples) is infeasible for $N > 100$

• 6.

  Chamber measurements overestimate field performance by 5–10 dB due to absence of multipath and interferers; field trials are the ground truth

• 7.

  The commercial sweet spot for RIS hardware is 2-bit phase + PIN-diode + thermal compensation — 80% of performance at 40% of continuous-phase panel cost

• 8.

  RIS calibration efficiency $\eta_{\text{cal}} = e^{-\sigma_\phi^2}$: $\sigma_\phi \leq 27°$ is sufficient for 80% efficiency; 2-bit alone achieves this with care