Phase Quantization: 1-bit, 2-bit, Continuous
Continuous Phases Are a Fiction
Chapter 1 optimized the received SNR over phases , a continuous set. Real RIS hardware supports only a finite set of phase states: a varactor driven by a 4-bit DAC realizes phase levels; a PIN-diode element might realize just 2. How much SNR is lost by rounding the "ideal" to the nearest available quantized level? The answer — surprisingly favorable — is derived here.
Definition: -Bit Phase Quantization
-Bit Phase Quantization
A -bit RIS element can realize distinct phase values, typically evenly spaced:
The quantized phase is the nearest element of :
The step size is .
Theorem: SNR Loss from -bit Phase Quantization
Under uniform-quantization with step and assuming the unquantized phase errors are uniform on , the expected received signal power degrades by the factor
The corresponding power penalty in dB is . In particular:
| Bits | Levels | dB loss | |
|---|---|---|---|
| 1 | 2 | ||
| 2 | 4 | ||
| 3 | 8 | ||
| 4 | 16 | ||
Quantization introduces a zero-mean phase error uniformly distributed in . The coherent sum (where is the aligned-phase amplitude and the phase error) has expected value . Thus the received amplitude is scaled by , and the power by .
Quantized sum
The received amplitude is , where and is the quantization error. Under uniform quantization the errors are approximately uniform on and independent across (for randomly-distributed optimal phases).
Expected amplitude
. Compute: .
Expected power
For large , . The first term dominates at large (coherent sum); the variance term is while the deterministic coherent part is . Hence .
Key Takeaway
Three bits of phase resolution lose only of coherent SNR. This is the practical argument for the industry standard of 3-bit RIS panels: the marginal gain from 3 → 4 bits () rarely justifies doubling the number of PIN diodes or control lines. Going down to 1 bit costs — an uncomfortable but survivable penalty for a cheap prototype.
Quantization Loss vs. Bits per Element
Vary the bit resolution and compare the quantized-phase sum against the continuous-phase ideal. The blue curve shows the theoretical prediction; the orange markers show a Monte-Carlo empirical loss for a random set of optimal phases.
Parameters
Rounding Continuous Phases onto a Discrete Grid
Example: A 1-bit RIS Prototype
Tang et al. (2021) built a 1-bit RIS with elements at 5.8 GHz. Compute the coherent-sum loss relative to a continuous-phase ideal. If the coherent-phase ideal gives received SNR, what is the 1-bit SNR?
Apply the $\eta_B$ formula
, so the power loss is .
1-bit SNR
. The 1-bit RIS loses almost but retains of the capacity at high SNR (since at high SNR, per-element scaling).
Practical note
The Tang prototype was a first-of-its-kind demonstration; its goal was to validate the coherent-combining law, not to maximize throughput. For that purpose, 1-bit was sufficient. Commercial deployments target at least 2 bits.
Nearest-Level Projection for -bit RIS
Complexity: per element, for the full RISNearest-level projection is the universal starting point, but it is not always optimal when the elements interact (e.g., if the objective is not a simple coherent sum). Chapter 8 revisits quantization as an integer program and compares direct discrete optimization with projection-from-continuous.
Common Mistake: Quantization Loss Is Not Additive
Mistake:
"Each element loses of its power, so the total loss is ."
Correction:
The quantization loss factor applies to the coherent sum, not to individual elements' power. Individual elements' reflected signal strength is unaffected — only the phase alignment is imperfect. The coherent-sum amplitude is reduced by , and the coherent-sum power by , uniformly for all . So the total coherent SNR becomes , not .
Quick Check
A 4-bit RIS loses approximately how much coherent SNR compared to a continuous-phase RIS?
(indistinguishable from continuous)
From the table: , giving .
How Many Bits Should a Real RIS Have?
The bit-depth choice is not about asymptotic SNR — it is about hardware complexity vs. calibration burden:
- 1-bit: two PIN diodes per element. Cheapest. loss. Good for prototypes, rapid beam steering, secrecy applications.
- 2-bit: four phase levels. Requires two diodes with carefully matched asymmetric loading. loss. Common in first-generation products.
- 3-bit: eight phase levels. Three diodes per element, or one varactor with a 3-bit DAC. loss. Industry default for mmWave RIS.
- Continuous (varactor with -bit DAC): no bit- quantization loss but significant calibration overhead (the voltage-phase curve is nonlinear and varies with temperature).
The sweet spot depends on the application: for high-rate communication, 3-bit is enough; for radar / ISAC where phase precision is paramount, prefer continuous; for deep-pocket IoT deployments, 1-bit remains the cost optimum.
- •
3-bit elements typically have 3 PIN diodes and 3 control lines per unit cell.
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Continuous (varactor) requires per-element DAC calibration for temperature stability.
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Control overhead scales as bits per configuration update.